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STA, timing closure, Senior Timng Engineer, Semiconductor MNC, Bangalore

STA, timing closure, Senior Timng Engineer, Semiconductor MNC, Bangalore

The Job involves handling timing analysis and closure of complex units of high performance processor chip. This role Involves working with global timing and PD leads as well as Logic Design and PD engineers and project managers in a matrix organization. ~Looking for professionals with hands on...

Updated: 2011-Dec-27 02:54 PM

Industry: Semiconductor, HardwareRole: Senior Timng Engineer

Experience Level: 6.0 to 12.0 yrsLocation: Bangalore (India)

Employer: Semiconductor MNC

Keywords: STA timing closure tcl perl

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Urgent opening for "Senior Physical Design Engineer (5+ yrs) : Bangalore"

Urgent opening for "Senior Physical Design Engineer (5+ yrs) : Bangalore"

~ Looking for professionals with hands on Physical Design experience ( ASICs, ASPs, Processors ). ~ The Job involves handling high performance unit level integration for processor chip. ~Responsibilities include, floorplanning, planning signal wires, pushing the data into lower level macros, ...

Updated: 2012-Apr-02 03:53 PM

Industry: Hardware, SemiconductorRole: Senior Physical Design Engineer

Experience Level: 5.0 to 12.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: floorplanning Place n Route timing closure physical verification power analysis signal issues

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Sr. Physical Design Engineers

Sr. Physical Design Engineers

Candidate will be responsible for sizing, physical design, timing closure and physical verification of very high speed digital IP blocks. Deliver the PD closed IP / testchip in a very tight schedule with high quality Work with digital/ Analog / layout designers across various global sites, to...

Updated: 2012-May-17 04:19 PM

Industry: SemiconductorRole: Sr. Physical Design Engineer

Experience Level: 5.0 to 10.0 yrsLocation: (India)

Employer: Client of Han Digital Solution

Keywords: Physical Design Timing closure analysis hands on experience with industry standard tools Expert in tool usage to optimize the placement resolving congestion clock expansion wiring issues

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Hiring "Physical Design Engineer/Lead", Client of Han Digital Solution (7 -12yrs) : Bangalore

Hiring "Physical Design Engineer/Lead", Client of Han Digital Solution (7 -12yrs) : Bangalore

~Looking for professionals with hands on Physical Design experience ( ASICs, ASPs, Processors ). The ~Job involves handling high performance unit level integration for processor chip. ~Responsibilities include, floorplanning, planning signal wires, pushing the data into lower level macros, ...

Updated: 2012-May-03 11:33 AM

Industry: SemiconductorRole: Physical Design Engineer/Lead

Experience Level: 7.0 to 12.0 yrsLocation: Bangalore (India)

Employer: Client of Han Digital Solution

Keywords: Floorplanning Place & Route Design Power analysis DRC Timing Closure Layout & Logic Design

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Floorplanning, Timing, Asic, Physical Design Engineers/ Leads, Fortune 50 Company, Bangalore

Floorplanning, Timing, Asic, Physical Design Engineers/ Leads, Fortune 50 Company, Bangalore

Joining Location: Bangalore Experience: 3~12 Yrs

Updated: 2012-Mar-25 10:10 AM

Role: Physical Design Engineers/ Leads

Experience Level: 3.0 to 12.0 yrsLocation: Bangalore (India)

Keywords: Floorplanning Timing Asic

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Test Engineer Job opening at USA (Full Time)

Test Engineer Job opening at USA (Full Time)

Role: SSE Responsibilities : Test Planning, Making Strategy Test Analysis, Scenario Preparation and review Test cases.

Updated: 2012-May-18 03:20 PM

Industry: IT ServicesRole: Test Engineer

Experience Level: 3.0 to 6.0 yrsLocation: Bloomington (United States)

Keywords: Automation Java Testing Eclipse Manual TEST

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STA, Floorplanning, Timing Engineers/ Leads, Fortune 50 company, Bangalore

Joining Location : Bangalore Experience: 3~12 Yrs

Updated: 2012-Mar-05 12:30 PM

Role: Timing Engineers/ Leads

Experience Level: 3.0 to 12.0 yrsLocation: Bangalore (India)

Employer: Fortune 50 company

Keywords: STA Floorplanning

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C++, Unix, Software Developer, Fortune 50 Company, Pune

C++, Unix, Software Developer, Fortune 50 Company, Pune

Software development and design Interface with team members and other programming teams Define Product strategy and provide leadership Act as a consultant on technical issues Produce high quality code, review and conduct unit tests Provide quality timely fixes to problems Evaluate recommend new...

Updated: 2012-Feb-23 03:59 PM

Industry: IT ProductsRole: Software Developer

Experience Level: 7.1 to 15.1 yrsLocation: Pune (India)

Keywords: C++ Unix Linux JNI RTP Real Time Protocol TCP media codecs

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