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IO Circuit design Engineer with Semiconductor MNC, Bangalore

Candidate will be responsible for circuit design and verification of various IO's including high speed IOs, DDR IOs Work on digital/ Analog / layout. Must have strong analog circuit design knowledge and hands on experience in transistor level design, layout and design closure. hands on...

Updated: 2011-Jul-07 02:32 PM

Industry: SemiconductorRole: IO Circuit design

Experience Level: 3.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: Circuit design

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Physical Design Engineer / Lead, Semiconductor MNC, Bangalore

Physical Design - Requirement 1: --------- ----------- ------------ ** Candidate will be responsible for sizing, physical design, timing closure and physical verification of very high speed digital IP blocks and testchip in sub 45nm technologies ** Deliver the PD closed IP / testchip in a...

Updated: 2011-Jul-07 02:08 PM

Industry: SemiconductorRole: Physical Design Engineer / Lead

Experience Level: 3.0 to 14.0 yrsLocation: Bangalore (India)

Keywords: placeroutePhysical DesignFloor planningDRCLVS

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Hiring "Physical Design Engineer/Lead", Client of Han Digital Solution (7 -12yrs) : Bangalore

~Looking for professionals with hands on Physical Design experience ( ASICs, ASPs, Processors ). The ~Job involves handling high performance unit level integration for processor chip. ~Responsibilities include, floorplanning, planning signal wires, pushing the data into lower level macros, ...

Updated: 2012-May-03 11:33 AM

Industry: SemiconductorRole: Physical Design Engineer/Lead

Experience Level: 7.0 to 12.0 yrsLocation: Bangalore (India)

Employer: Client of Han Digital Solution

Keywords: Floorplanning Place & Route Design Power analysis DRC Timing Closure Layout & Logic Design

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System Verification Testing, Fortune 50 company, Bangalore

Job description Test Engineer with 4+ years of exp in S/W Testing/QA in a product development environment, Very good at Test planning, Test cases writing and execution skills, Rich experience in functional, regression testing, system testing, defect management Software configuration management....

Updated: 2011-Dec-27 02:30 PM

Industry: IT ProductsRole: System Verification Testing

Experience Level: 4.0 to 8.0 yrsLocation: Bangalore (India)

Employer: Fortune 50 company

Keywords: UML OOAD System Testing C++/Java

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Unix System Admin - Business Operations Professional, Fortune 50 company, Pune

Employment Type: Permanent with client. Position: Business Operations Professional . Location: Pune.

Updated: 2011-Dec-31 10:22 AM

Industry: IT ServicesRole: Business Operations Professional

Experience Level: 5.0 to 8.0 yrsLocation: (India)

Employer: Fortune 50 company

Keywords: Oracle DBA Unix System Admin

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Oracle DBA, Unix System Admin, Business Operations Professional, Fortune 50 company

Greetings to you, This is Syed from HAN DIGITAL SOLUTIONS (p) Ltd., Bangalore. We, Han Digital Solution provide dedicated placement services to IT and IT Related Product Companies. Currently we do have requirement for ' Business Operations Professional ' with one of our US Based MNC Client....

Updated: 2011-Dec-31 09:52 AM

Industry: IT ServicesRole: Business Operations Professional

Experience Level: 5.0 to 8.0 yrsLocation: (India)

Employer: Fortune 50 company

Keywords: Oracle DBA Unix System Admin

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Sr. Physical Design Engineers

Candidate will be responsible for sizing, physical design, timing closure and physical verification of very high speed digital IP blocks. Deliver the PD closed IP / testchip in a very tight schedule with high quality Work with digital/ Analog / layout designers across various global sites, to...

Updated: 2012-May-17 04:19 PM

Industry: SemiconductorRole: Sr. Physical Design Engineer

Experience Level: 5.0 to 10.0 yrsLocation: (India)

Employer: Client of Han Digital Solution

Keywords: Physical Design Timing closure analysis hands on experience with industry standard tools Expert in tool usage to optimize the placement resolving congestion clock expansion wiring issues

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Circuit Design Engineer/lead, Semiconductor MNC(6+yrs):Bangalore

~ Candidate will be responsible for circuit verification design of high speed SerDes IP blocks. ~ Deliver the layout closed IP / testchip in a tight schedule with high quality ~ Work with digital/ Analog / layout designers across various global sites, to integrate the IP block

Updated: 2012-Apr-06 03:36 PM

Industry: SemiconductorRole: Circuit Design Engineer/lead

Experience Level: 6.0 to 12.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: Circuit Design analog analog macros spec-GDS amplifier Voltage regulator PLL

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Verification Engineer / Lead / Manager ( 4 to 14 Yrs ) Bangalore Location, Semiconductor MNC, Bangalore

Verification Engineer( 5-7 years) Will contribute to the development of test plan, verification infrastructure development, verification of complex processor core functions and sign off of the design for tapeout. Will ensure adequate levels of thoroughness and quality in verification....

Updated: 2011-Jul-07 02:07 PM

Industry: SemiconductorRole: Verification Engineer / Lead / Manager ( 4 to 14 Yrs ) Bangalore Location

Experience Level: 4.0 to 14.0 yrsLocation: Bangalore (India)

Keywords: verificationSpecmansystem verilog c++

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Processor Verification Engineers, Semiconductor MNC (3-8 yrs) : Bangalore

Working on verification of modules/units for mainframe/server class processors. Will be responsible building the verification environment, testcase development, simulations, debug, coverage analysis etc. Will be responsible for the quality of verification environment, testcases and making the...

Updated: 2012-Jan-31 12:39 PM

Industry: Semiconductor, HardwareRole: Processor Verification Engineers

Experience Level: 3.0 to 8.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: System Verilog

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maximo, java, Integration, Functional Consultant, Fortune 50 company

Joining location: Bangalore, Pune Experience: 4 - 9 Yrs

Updated: 2011-Jul-06 10:02 AM

Industry: IT Products, IT ServicesRole: Functional Consultant

Experience Level: 4.0 to 9.0 yrsLocation: (India)

Employer: Fortune 50 company

Keywords: maximo java Integration design

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Looking for Senior Layout Design Engineer (7-9 yrs) : Bangalore for Leading Semiconductor MNC

VLSI circuit layout using industry leading tools, in particular CADENCE Virtuoso XL. Familiar with custom layout, layout verification methodologies, and design for yield and manufacturability. Familiar with Cadence routing tools such as IC Craftsman is a plus. Ability to write CADENCE “SKILL”...

Updated: 2012-Mar-30 10:51 AM

Industry: SemiconductorRole: Senior Layout Engineer

Experience Level: 7.0 to 9.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: Custom Layout Design layout verification Cadence Virtuoso cadence skill programming

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Processor Verification Engineers Leading Semiconductor MNC (4-12 yrs) : Bangalore

Working on verification of modules/units for mainframe/server class processors. Will be responsible building the verification environment, testcase development, simulations, debug, coverage analysis etc. Will be responsible for the quality of verification environment, testcases and making the...

Updated: 2012-Mar-30 10:51 AM

Industry: Semiconductor, HardwareRole: Processor Verification Engineers

Experience Level: 4.0 to 12.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: System Verilog C++ Modelsim ncsim VHDL

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Datastage Architect, Client of Han Digital Solution, Bangalore Mumbai Pune Hyderabad New Delhi / NCR Chennai

- Evaluate RFP’s and respond with DI solution that includes Business, Software and Hardware solution - Lead DI Solution conceptualization, architecture, development and demonstration of solutions - Responsible for Presales of DI Solutions - Design, Develop and Demonstrate DI PoCs

Updated: 2012-May-22 09:35 AM

Industry: IT ServicesRole: Datastage Integration Architect

Experience Level: 8.0 to 15.0 yrsLocation: Bangalore Mumbai Pune Hyderabad New Delhi / NCR Chennai (India)

Employer: Client of Han Digital Solution

Keywords: design DataStage Integration

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Device /Compact Modeling Engineer/Lead/Manager, Semiconductor MNC, Bangalore

~ Manage and lead a strong technical team to effectively ~ Develop compact models for FETs and passive devices like diodes, resistors, inductors , capacitors ~ Design Test sites and define test programs for RF/DC Characterization ~ Work closely with globally integrated team of device modelers,...

Updated: 2012-Mar-30 11:01 AM

Industry: SemiconductorRole: Device /Compact Modeling Engineer/Lead/Manager

Experience Level: 5.0 to 12.0 yrsLocation: Bangalore (India)

Employer: Semiconductor MNC

Keywords: RF Design VLSI Circuit Design Charaterisation Semiconductor Device Physics

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Principal Engineer (C++), Fortune 50 Company

Position : Principal Engineer (C++) Years of Experience : 10Yrs+ Location : Bangalore This person will be a Principal Engineer on the Database Catalog Services product. The person working closely DB engine component owners shall lead the team to strategize, design implement API, services,...

Updated: 2012-Mar-06 05:15 PM

Industry: IT ProductsRole: Principal Engineer (C++)

Experience Level: 9.5 to 15.0 yrsLocation: (India)

Keywords: C++ Design metadata Architecture API RDBMS

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DFT Manager Jobs in Bangalore

Looking for Candidates with Relevant DFT experience And Good Experience in Leading and Managing Teams With Excellent problem solving skills Excellent communication and teamwork skills and good English is required.

Updated: 2012-May-13 01:31 PM

Industry: SemiconductorRole: DFT Manager

Experience Level: 8.0 to 12.0 yrsLocation: (India)

Employer: Client of Han Digital Solution

Keywords: DFT Design For test ATPG BIST Scan Insertion Stuck At

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DFT Lead Jobs in Bangalore

~ Looking for Candidates with Relevant DFT experience ~ Generate Tester Manufacturing Data for ASICs / Processors with a focus on generating patterns for transition faults and stuck faults. ~ Run simulations to verify that patterns will work ~ Knowledge/experience of transition faults and...

Updated: 2012-May-13 01:24 PM

Industry: SemiconductorRole: DFT Lead

Experience Level: 7.0 to 12.0 yrsLocation: (India)

Employer: Client of Han Digital Solution

Keywords: DFT Design For test ATPG BIST Scan Insertion Stuck At

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Opportunity with a Leading Client for Oracle Identity Manager in Bangalore

CA identity manager design, development, customization exp-mandatory (Also having admin+developer exp is considered) Java/J2EE exp – preferred LDAP, PKI, SSSL, JNDI, RSA BSAFE exp - preferred

Updated: 2012-Feb-28 05:28 PM

Industry: IT ServicesRole: Oracle Identity Manager

Experience Level: 5.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: Design Development Customisation Java J2EE LDAP PKI SSL JNDI RSA BSAFE

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Opening for C++ Developer, Client of Han Digital Solution, chennai/bangalore

Perform high quality software analysis, design, development, testing and maintenance for the client’s core technology platform Be part of the l Risk Product development to Implement new tools and features using C++ and Java in Apache/Linux environment. Enhance and maintain existing product...

Updated: 2012-May-17 04:04 PM

Industry: IT ProductsRole: C++ Developer

Experience Level: 3.0 to 15.0 yrsLocation: chennai/bangalore (India)

Employer: Client of Han Digital Solution

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large scale system design Jobs

Keywords: Circuit design

Keywords: placeroutePhysical DesignFloor planningDRCLVS

Keywords: Floorplanning Place & Route Design Power analysis DRC Timing Closure Layout & Logic Design

Keywords: UML OOAD System Testing C++/Java

Keywords: Oracle DBA Unix System Admin

Keywords: Oracle DBA Unix System Admin

Keywords: Physical Design Timing closure analysis hands on experience with industry standard tools Expert in tool usage to optimize the placement resolving congestion clock expansion wiring issues

Keywords: Circuit Design analog analog macros spec-GDS amplifier Voltage regulator PLL

Keywords: verificationSpecmansystem verilog c++

Keywords: System Verilog

Keywords: maximo java Integration design

Keywords: Custom Layout Design layout verification Cadence Virtuoso cadence skill programming

Keywords: System Verilog C++ Modelsim ncsim VHDL

Keywords: design DataStage Integration

Keywords: RF Design VLSI Circuit Design Charaterisation Semiconductor Device Physics

Keywords: C++ Design metadata Architecture API RDBMS

Keywords: DFT Design For test ATPG BIST Scan Insertion Stuck At

Keywords: DFT Design For test ATPG BIST Scan Insertion Stuck At

Keywords: Design Development Customisation Java J2EE LDAP PKI SSL JNDI RSA BSAFE

Keywords: C++ UNIX Datastructure design pattern