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*SAP Technical Consultant Job opening with product base company at Bangalore

Role: Technical Consultant Responsibilities: As a member of the global team Candidate has to work on IBM i, SAP applications. SAP HANA appliance support (last level support, dev support) Support SAP HANA customers Problem determination, debugging, fixing Maintain and issue technical...

Updated: 2012-May-18 03:21 PM

Industry: IT ProductsRole: SAP Technical Consultant

Experience Level: 10.0 to 16.0 yrsLocation: Bangalore (India)

Employer: Fortune 50 company

Keywords: SAP Hana Intel Hardware Unix System X Hardware GPFS

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Urgent opening for "Senior Physical Design Engineer (5+ yrs) : Bangalore"

Urgent opening for "Senior Physical Design Engineer (5+ yrs) : Bangalore"

~ Looking for professionals with hands on Physical Design experience ( ASICs, ASPs, Processors ). ~ The Job involves handling high performance unit level integration for processor chip. ~Responsibilities include, floorplanning, planning signal wires, pushing the data into lower level macros, ...

Updated: 2012-Apr-02 03:53 PM

Industry: Hardware, SemiconductorRole: Senior Physical Design Engineer

Experience Level: 5.0 to 12.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: floorplanning Place n Route timing closure physical verification power analysis signal issues

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DFT Lead Engineer (6-8yrs), Semiconductor MNC : Bangalore

DFT Lead Engineer (6-8yrs), Semiconductor MNC : Bangalore

~ Generate Tester Manufacturing Data for ASICs / Processors with a focus on generating patterns for transition faults and stuck faults. ~ Run simulations to verify that patterns will work ~ Knowledge/experience of transition faults and techniques like ASST, path delay testing, small delay...

Updated: 2012-Apr-02 12:50 PM

Industry: Hardware, SemiconductorRole: DFT Lead Engineer

Experience Level: 6.0 to 8.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: DFT scan insertion ATPG ABIST LBIST MBIST

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Processor Verification Engineers Leading Semiconductor MNC (4-12 yrs) : Bangalore

Processor Verification Engineers Leading Semiconductor MNC (4-12 yrs) : Bangalore

Working on verification of modules/units for mainframe/server class processors. Will be responsible building the verification environment, testcase development, simulations, debug, coverage analysis etc. Will be responsible for the quality of verification environment, testcases and making the...

Updated: 2012-Mar-30 10:51 AM

Industry: Semiconductor, HardwareRole: Processor Verification Engineers

Experience Level: 4.0 to 12.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: System Verilog C++ Modelsim ncsim VHDL

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Processor Verification Engineers, Semiconductor MNC (3-8 yrs) : Bangalore

Processor Verification Engineers, Semiconductor MNC (3-8 yrs) : Bangalore

Working on verification of modules/units for mainframe/server class processors. Will be responsible building the verification environment, testcase development, simulations, debug, coverage analysis etc. Will be responsible for the quality of verification environment, testcases and making the...

Updated: 2012-Jan-31 12:39 PM

Industry: Semiconductor, HardwareRole: Processor Verification Engineers

Experience Level: 3.0 to 8.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: System Verilog

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DFT Lead Engineers (5- 10 yrs) : Bangalore

DFT Lead Engineers (5- 10 yrs) : Bangalore

Job Description:- ~ Generate Tester Manufacturing Data for ASICs / Processors with a focus on generating patterns for transition faults and stuck faults. ~ Run simulations to verify that patterns will work ~ Knowledge/experience of transition faults and techniques like ASST, path delay testing,...

Updated: 2011-Dec-27 03:01 PM

Industry: Semiconductor, HardwareRole: DFT Lead Engineer

Experience Level: 5.0 to 10.0 yrsLocation: (India)

Employer: Semiconductor MNC

Keywords: DFT scan insertion ATPG

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STA, timing closure, Senior Timng Engineer, Semiconductor MNC, Bangalore

STA, timing closure, Senior Timng Engineer, Semiconductor MNC, Bangalore

The Job involves handling timing analysis and closure of complex units of high performance processor chip. This role Involves working with global timing and PD leads as well as Logic Design and PD engineers and project managers in a matrix organization. ~Looking for professionals with hands on...

Updated: 2011-Dec-27 02:54 PM

Industry: Semiconductor, HardwareRole: Senior Timng Engineer

Experience Level: 6.0 to 12.0 yrsLocation: Bangalore (India)

Employer: Semiconductor MNC

Keywords: STA timing closure tcl perl

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