Floorplanning, Timing, Asic, Physical Design Engineers/ Leads, Fortune 50 Company, Bangalore

Joining Location: Bangalore

Experience: 3~12 Yrs

Job Description for PD Engineer/Lead:

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~Looking for professionals with hands on Physical Design experience (ASICs, ASPs, Processors).

~The Job involves handling high performance unit level integration for processor chip.

~Responsibilities include, floor planning, planning signal wires, pushing the data into lower level macros, physical integration of the lower level abstracts at the next higher level, timing closure, clean up signal and design integrity issues, physical verification and complete delivery of the high quality

~ Integrated unit to the chip level.

~Hands on exposure to timing closure techniques is a must.

~This role Involves working with global PD and timing leads, PD engineers and project managers in a matrix organization.

~Individual must have hands on PD experience with industry standard tools.

~Exposure to Cadence virtuoso tool will be added advantage.

~Candidates with Processor implementation back ground are preferred.

~Looking for candidates with more than4 years of relevant PD experience